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LTC3412A 3A, 4MHz, Monolithic Synchronous Step-Down Regulator
FEATURES

DESCRIPTIO

High Efficiency: Up to 95% 3A Output Current Low Quiescent Current: 64A Low RDS(ON) Internal Switch: 77m 2.25V to 5.5V Input Voltage Range Programmable Frequency: 300KHz to 4MHz 2% Output Voltage Accuracy 0.8V Reference Allows Low Output Voltage Selectable Forced Continuous/Burst Mode(R) Operation with Adjustable Burst Clamp Synchronizable Switching Frequency Low Dropout Operation: 100% Duty Cycle Power Good Output Voltage Monitor Overtemperature Protected Available in 16-Lead Exposed Pad TSSOP and QFN Packages
The LTC(R)3412A is a high efficiency monolithic synchronous, step-down DC/DC converter utilizing a constant frequency, current mode architecture. It operates from an input voltage range of 2.25V to 5.5V and provides a regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. The internal synchronous power switch with 77m on-resistance increases efficiency and eliminates the need for an external Schottky diode. Switching frequency is set by an external resistor or can be synchronized to an external clock. 100% duty cycle provides low dropout operation extending battery life in portable systems. OPTI-LOOP(R) compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The LTC3412A can be configured for either Burst Mode operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while Burst Mode operation provides high efficiency by reducing gate charge losses at light loads. In Burst Mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the application requirements.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.
APPLICATIO S

Point-of-Load Regulation Notebook Computers Portable Instruments Distributed Power Systems
TYPICAL APPLICATIO
22F VIN 3.3V PVIN SVIN 2.2M 294k RT
Efficiency and Power Loss
100 95 EFFICIENCY 10000 100000
PGOOD LTC3412A SW 0.47H
EFFICIENCY (%)
90
VOUT 2.5V AT 3A COUT 100F x2
85 80 75 70 65 60 POWER LOSS 10 100 1000
RUN/SS 1000pF 12.1k ITH SYNC/MODE 820pF
PGND SGND VFB
69.8k 115k
392k
3412A F01a
55 50 0.01 0.1 1 LOAD CURRENT (A) 1 10
3412A F01b
Figure 1. 2.5V/3A Step-Down Regulator
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POWER LOSS (mW)
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LTC3412A
ABSOLUTE
(Note 1)
AXI U RATI GS
Operating Ambient Temperature Range (Note 2) ...............................................- 40C to 85C Junction Temperature (Note 5) ............................. 125C Lead Temperature (Soldering, 10 sec) .................. 300C
Input Supply Voltage .................................... -0.3V to 6V ITH, RUN/SS, VFB, PGOOD, SYNC/MODE Voltages ....................................-0.3 to VIN SW Voltages ..................................-0.3V to (VIN + 0.3V)
PI CO FIGURATIO
TOP VIEW SVIN PGOOD ITH VFB RT SYNC/MODE RUN/SS SGND 1 2 3 4 5 6 7 8 17 16 PVIN 15 SW 14 SW 13 PGND 12 PGND 11 SW 10 SW 9 PVIN RUN/SS 1 SGND 2 PVIN 3 SW 4
SYNC/MODE
VFB
16 15 14 13 12 PGOOD 17 11 SVIN 10 PVIN 9 5 SW 6 PGND 7 PGND 8 SW SW
FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 38C/W, JC = 10C/W EXPOSED PAD (PIN 17) IS SGND MUST BE SOLDERED TO PCB
UF PACKAGE 16-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 34C/W, JC = 1C/W EXPOSED PAD (PIN 17) IS GND, MUST BE CONNECTED TO PCB
ORDER I FOR ATIO
LEAD FREE FINISH LTC3412AEFE#PBF LTC3412AIFE#PBF LTC3412AEUF#PBF LTC3412AIUF#PBF LEAD BASED FINISH LTC3412AEFE LTC3412AIFE LTC3412AEUF LTC3412AIUF TAPE AND REEL
PART MARKING* 3412AEFE 3412AIFE 3412A 3412A PART MARKING* 3412AEFE 3412AIFE 3412A 3412A
PACKAGE DESCRIPTION 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP 16-Lead (4mm x 4mm) Plastic QFN 16-Lead (4mm x 4mm) Plastic QFN PACKAGE DESCRIPTION 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP 16-Lead (4mm x 4mm) Plastic QFN 16-Lead (4mm x 4mm) Plastic QFN
ITH
RT
LTC3412AEFE#TRPBF LTC3412AIFE#TRPBF LTC3412AEUF#TRPBF LTC3412AIUF#TRPBF TAPE AND REEL LTC3412AEFE#TR LTC3412AIFE#TR LTC3412AEUF#TR LTC3412AIUF#TR
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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TOP VIEW
TEMPERATURE RANGE -40C to 85C -40C to 85C -40C to 85C -40C to 85C TEMPERATURE RANGE -40C to 85C -40C to 85C -40C to 85C -40C to 85C
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LTC3412A
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 3.3V unless otherwise specified.
SYMBOL SVIN VFB IFB VFB VLOADREG VPGOOD RPGOOD IQ PARAMETER Signal Input Voltage Range Regulated Feedback Voltage Voltage Feedback Leakage Current Reference Voltage Line Regulation Output Voltage Load Regulation Power Good Range Power Good Pull-Down Resistance Input DC Bias Current Active Current Sleep Shutdown Switching Frequency Switching Frequency Range SYNC Capture Range RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET Peak Current Limit Undervoltage Lockout Threshold SW Leakage Current RUN Threshold RUN/SS Leakage Current VRUN = 0V, VIN = 5.5V 0.5 (Note 4) VFB = 0.78V, VITH = 1V VFB = 1V, VITH = 0V VRUN = 0V, VMODE = 0V ROSC = 294k (Note 6) (Note 6) ISW = 1A (Note 7) ISW = -1A (Note 7) 4.5 1.75 0.88 0.3 0.3 77 65 6 2 0.1 0.65 2.25 1 0.8 1 VIN = 2.7V to 5.5V (Note 3) Measured in Servo Loop, VITH = 0.36V Measured in Servo Loop, VITH = 0.84V (Note 3) CONDITIONS MIN 2.25 0.784 0.800 0.1 0.04 0.02 -0.02 7.5 120 250 64 0.02 1 TYP MAX 5.5 0.816 0.2 0.2 0.2 -0.2 9 200 330 80 1 1.1 4 4 110 90 UNITS V V A %V % % % A A A MHz MHz MHz m m A V A V A
ELECTRICAL CHARACTERISTICS
fOSC fSYNC RPFET RNFET ILIMIT VUVLO ILSW VRUN IRUN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3412AE is guaranteed to meet performance specifications from 0C to 85C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3412AI is guaranteed to meet performance specifications over the full -40C to 85C operating temperature range.
Note 3: The LTC3412A is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. Note 5: TJ is calculated from the ambient temperature TA and power dissipation as follows: LTC3412AFE: TJ = TA + PD (38C/W) LTC3412AUF: TJ = TA + PD (34C/W) Note 6: 4MHz operation is guaranteed by design and not production tested. Note 7: Switch on resistance is guaranteed by design and test condition in the UF package and by final test correlation in the FE package.
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LTC3412A
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
100 90 Burst Mode 80 OPERATION EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 VIN = 3.3V VOUT = 2.5V FIGURE 4 CIRCUIT 0.1 1 LOAD CURRENT (A) 10
3412A GO1
80 75 70 65 60 55 50 0.01 VOUT = 2.5V FIGURE 4 CIRCUIT 0.1 1 LOAD CURRENT (A) 10
3412A GO2
EFFICIENCY (%)
FORCED CONTINUOUS
Efficiency vs Input Voltage
94 92 1A 90 EFFICIENCY (%) 0.1A 88 86 84 3A 82 80 2.5 EFFICIENCY (%) 93 92 91 90 89 88 3.0 4.0 INPUT VOLTAGE (V) 3.5 4.5 5.0
3412A GO4
FIGURE 4 CIRCUIT
0.47H
VOUT/VOUT (%)
Burst Mode Operation
VOUT 20mV/DIV
INDUCTOR CURRENT 1A/DIV
FIGURE 4 CIRCUIT 5s/DIV
3412A GO7
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UW
Efficiency vs Load Current, Burst Mode Operation
100 95 90 85 VIN = 5V VIN = 3.3V 100 90 80 70 60 50 40 30 20 10
Efficiency vs Load Current, Forced Continuous Operation
VIN = 3.3V VIN = 5V
VOUT = 2.5V FIGURE 4 CIRCUIT 0.1 1 LOAD CURRENT (A) 10
3412A GO3
0 0.01
Efficiency vs Frequency
96 95 94 1H 0.22H -0.2 -0.3 -0.4 -0.5 -0.6 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (MHz) 3.5 4.0 FIGURE 4 CIRCUIT VIN = 3.3V 0 -0.1
Load Regulation
FIGURE 4 CIRCUIT VIN = 3.3V
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0
0.5
1.0 1.5 2.0 LOAD CURRENT (A)
2.5
3.0
3412A GO5
3412A GO6
Output Voltage Ripple
Load Step Transient Burst Mode Operation
BURST MODE 20mV/DIV PULSE SKIPPING 20mV/DIV FORCED CONTINUOUS 20mV/DIV
VOUT 100mV/DIV
INDUCTOR CURRENT 2A/DIV
VIN = 3.3V 5s/DIV VOUT = 2.5V FIGURE 4 CIRCUIT
3412A GO8
VIN = 3.3V 40s/DIV VOUT = 2.5V F = 1MHz LOAD STEP = 50mA TO 2A FIGURE 4 CIRCUIT
3412A GO9
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LTC3412A
TYPICAL PERFOR A CE CHARACTERISTICS
Load Step Transient Forced Continuous
VOUT 2V/DIV VOUT 100mV/DIV VREF (V)
INDUCTOR CURRENT 2A/DIV
40s/DIV VIN = 3.3V VOUT =2.5V F = 1MHz LOAD STEP = 0A TO 3A FIGURE 4 CIRCUIT
Switch On-Resistance vs Input Voltage
100 95 90 ON-RESISTANCE (m) ON-RESISTANCE (m) 85 80 75 70 65 60 55 50 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0
3412A G13
100 80 60 NFET 40 20 0 -40 -20
SWITCH LEAKAGE CURRENT (nA)
PFET
NFET
5000 4500 4000 FREQUENCY (kHz)
Frequency vs ROSC
VIN = 3.3V
FREQUENCY (kHz)
3000 2500 2000 1500 1000 500 0 40 140 240 340 440 540 640 740 840 940 ROSC (k)
3412A G16
FREQUENCY (kHz)
3500
UW
Start-Up Transient
0.7975 0.7970 0.7965 0.7960 RUN/SS 2V/DIV INDUCTOR CURRENT 2A/DIV 0.7955 0.7950 0.7945 0.7940 0.7935 1ms/DIV VIN = 3.3V VOUT =2.5V LOAD STEP = 2A FIGURE 4 CIRCUIT
VREF vs Temperature
VIN = 3.3V
0.7930 -45 -25
3412A G11
-5
15 35 55 75 TEMPERATURE (C)
95
115
3412A G12
3412A G10
Switch On-Resistance vs Temperature
120 VIN = 3.3V 50 45 40 35 30 25 20 15 10 5 0 0 20 40 60 80 TEMPERATURE (C) 100 120
3412A G14
Switch Leakage Current vs Input Voltage
PFET
PFET
NFET 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5
3412A G15
Frequency vs Input Voltage
1060 ROSC = 294k 1050 1040 1030 1020 1010 1000 990 2.5 1020
Frequency vs Temperature
VIN = 3.3V 1015 ROSC = 294k 1010 1005 1000 995 990 985 980 975
3.0
4.0 4.5 3.5 INPUT VOLTAGE (V)
5.0
5.5
970 -40 -20
0
20 40 60 80 TEMPERATURE (C)
100 120
3412A G18
3412A G17
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LTC3412A
TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current vs Input Voltage
350 300 QUIESCENT CURRENT (A) 250 200 150 100 SLEEP 50 0 2.5 ACTIVE QUIESCENT CURRENT (A) 350 VIN = 3.3V 300 250 200 150 100 50 0 -40 -20 ACTIVE
MAXIMUM PEAK INDUCTOR CURRENT (mA)
3.0
3.5 4.0 4.5 INPUT VOLTAGE (V)
PEAK INDUCTOR CURRENT (A)
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UW
5.0
3412A G19
Quiescent Current vs Temperature
4000 3500 3000 2500 2000 1500 1000 500
Minimum Peak Inductor Current vs Burst Clamp Voltage
SLEEP
5.5
0
20
40
60
80
100 120
3412A G20
0 0.1
0.2
0.3
TEMPERATURE (C)
0.4 0.5 VBURST (V)
0.6
0.7
3412A G21
Peak Current vs Input Voltage
8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 2.25 2.75 3.25 3.75 4.25 INPUT VOLTAGE (V) 4.75
3412A G22
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LTC3412A
PI FU CTIO S
SVIN (Pin 1/Pin 11): Signal Input Supply. Decouple this pin to SGND with a capacitor. PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of regulation point. ITH (Pin 3/Pin 13): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is from 0.2V to 1.4V with 0.4V corresponding to the zero-sense voltage (zero current). VFB (Pin 4/Pin 14): Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output. RT (Pin 5/Pin 15): Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. SYNC/MODE (Pin 6/Pin 16): Mode Select and External Clock Synchronization Input. To select forced continuous, tie to SVIN. Connecting this pin to a voltage between 0V and 1V selects Burst Mode operation with the burst clamp set to the pin voltage.
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(FE Package/UHF Package)
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input. Forcing this pin below 0.5V shuts down the LTC3412A. In shutdown all functions are disabled drawing < 1A of supply current. A capacitor to ground from this pin sets the ramp time to full output current. SGND (Pin 8/Pin 2): Signal Ground. All small-signal components, compensation components and the exposed pad on the bottom side of the IC should connect to this ground, which in turn connects to PGND at one point. PVIN (Pins 9, 16/Pins 3, 10): Power Input Supply. Decouple this pin to PGND with a capacitor. SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node Connection to the Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect this pin close to the (-) terminal of CIN and COUT. Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be soldered to PCB for electrical connection and rated thermal performance.
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LTC3412A
FUNCTIONAL BLOCK DIAGRA
SVIN 1 SGND 8 ITH 3
VOLTAGE REFERENCE 0.8V
+ -
VFB 4
-
ERROR AMPLIFIER SYNC/MODE
0.74V
+ -
+ -
+
+
RUN/SS 7 RUN 0.86V PGOOD 2 NMOS CURRENT COMPARATOR
-
OPERATIO
Main Control Loop The LTC3412A is a monolithic, constant-frequency, currentmode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the current comparator trips and turns off the top power MOSFET. The peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the ITH pin. The error amplifier adjusts the voltage on the ITH pin by
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PVIN 9 16 SLOPE COMPENSATION RECOVERY BCLAMP PMOS CURRENT COMPARATOR
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+ -
P-CH
BURST COMPARATOR 10 SLOPE COMPENSATION 11 SW 14 15 N-CH LOGIC
OSCILLATOR
+ - - +
REVERSE CURRENT COMPARATOR 5 RT 6 SYNC/MODE
12 PGND 13
3412 FBD
comparing the feedback signal from a resistor divider on the VFB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The bottom current limit is set at -1.3A for forced continuous mode and 0A for Burst Mode operation.
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LTC3412A
OPERATIO
The operating frequency is externally set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 4MHz. Overvoltage and undervoltage comparators will pull the PGOOD output low if the output voltage comes out of regulation by 7.5%. In an overvoltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the overvoltage condition clears or the bottom MOSFET's current limit is reached. Forced Continuous Mode Connecting the SYNC/MODE pin to SVIN will disable Burst Mode operation and force continuous current operation. At light loads, forced continuous mode operation is less efficient than Burst Mode operation, but may be desirable in some applications where it is necessary to keep switching harmonics out of a signal band. The output voltage ripple is minimized in this mode. Burst Mode Operation Connecting the SYNC/MODE pin to a voltage in the range of 0V to 1V enables Burst Mode operation. In Burst Mode operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the minimum peak inductor current is externally set by the voltage on the SYNC/MODE pin and the voltage on the ITH pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. When the average inductor current is greater than the load current, the voltage on the ITH pin drops. As the ITH voltage falls below 150mV, the burst comparator trips and enables sleep mode. During sleep mode, the top power MOSFET is held off and the ITH pin is disconnected from the output of the error amplifier. The majority of the internal circuitry is also turned off to reduce the quiescent current to 64A while the load current is solely supplied by the output capacitor. When the output voltage drops, the ITH pin is reconnected to the output of the error amplifier and the top power MOSFET along with all the internal circuitry is
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switched back on. This process repeats at a rate that is dependent on the load demand. Pulse Skipping operation is implemented by connecting the SYNC/MODE pin to ground. This forces the burst clamp level to be at 0V. As the load current decreases, the peak inductor current will be determined by the voltage on the ITH pin until the ITH voltage drops below 400mV. At this point, the peak inductor current is determined by the minimum on-time of the current comparator. If the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. Frequency Synchronization The internal oscillator of the LTC3412A can be synchronized to an external clock connected to the SYNC/MODE pin. The frequency of the external clock can be in the range of 300kHz to 4MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. During synchronization, the burst clamp is set to 0V, and each switching cycle begins at the falling edge of the clock signal. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC3412A is designed to operate down to an input supply voltage of 2.25V. One important consideration at low input supply voltages is that the RDS(ON) of the P-channel and N-channel power switches increases. The user should calculate the power dissipation when the LTC3412A is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded.
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LTC3412A
APPLICATIO S I FOR ATIO
Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the LTC3412A, however, slope compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range of duty cycles. This keeps the maximum output current relatively constant regardless of duty cycle. Short-Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. To prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. If the inductor valley current increases larger than 4.4A, the top power MOSFET will be held off and switching cycles will be skipped until the inductor current is reduced. The basic LTC3412A application circuit is shown in Figure 1. External component selection is determined by the maximum load current and begins with the selection of the operating frequency and inductor value followed by CIN and COUT. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency of the LTC3412A is determined by an external resistor that is connected between pin RT and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: ROSC = 3.08 * 1011 () - 10k f
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Although frequencies as high as 4MHz are possible, the minimum on-time of the LTC3412A imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns; therefore, the minimum duty cycle is equal to 100 * 110ns * f(Hz). Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current IL increases with higher VIN or VOUT and decreases with higher inductance. IL = VOUT fL 1- VOUT VIN Having a lower ripple current reduces the core losses in the inductor, the ESR losses in the output capacitors, and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is IL = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: L= VOUT f IL(MAX) 1- VOUT VIN(MAX) The inductor value will also have an effect on Burst Mode operation. The transition to low current operation begins when the peak inductor current falls below a level set by the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase.
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LTC3412A
APPLICATIO S I FOR ATIO
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price verus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko, and Sumida. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal wave current at the source of the top MOSFET. To prevent large voltage transients from occurring, a low ESR input capacitor sized for the maximum RMS current should be used. The maximum RMS current is given by: IRMS =IOUT(MAX) VOUT VIN VIN -1 VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. The selection of COUT is determined by the effective series resistance (ESR) that is required to minimize voltage ripple and load step transients as well as the amount of bulk
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capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, VOUT, is determined by: VOUT IL ESR + 1 8fCOUT The output ripple is highest at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
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LTC3412A
APPLICATIO S I FOR ATIO
Output Voltage Programming
The output voltage is set by an external resistive divider according to the following equation: VOUT = 0.8V 1+ R2 R1
The resistive divider allows pin VFB to sense a fraction of the output voltage as shown in Figure 2.
VOUT R2 VFB LTC3412A SGND
3412A F02
R1
Figure 2. Setting the Output Voltage
Burst Clamp Programming If the voltage on the SYNC/MODE pin is less than VIN by 1V, Burst Mode operation is enabled. During Burst Mode Operation, the voltage on the SYNC/MODE pin determines the burst clamp level, which sets the minimum peak inductor current, IBURST. To select the burst clamp level, use the graph of Minimum Peak Inductor Current vs Burst Clamp Voltage in the Typical Performance Characteristics section. VBURST is the voltage on the SYNC/MODE pin. IBURST can only be programmed in the range of 0A to 6A. For values of VBURST greater than 1V, IBURST is set at 6A. For values of VBURST less than 0.4V, IBURST is set at 0A. As the output load current drops, the peak inductor currents decrease to keep the output voltage in regulation. When the output load current demands a peak inductor current that is less than IBURST, the burst clamp will force the peak inductor current to remain equal to IBURST regardless of further reductions in the load current. Since the average inductor current is greater than the output load current, the voltage on the ITH pin will decrease. When the ITH voltage drops to 150mV, sleep mode is enabled in which both power MOSFETs are shut off along with most of the circuitry to minimize power consumption. All circuitry is turned back on and the power MOSFETs begin switching again when the output voltage drops out of regulation.
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The value for IBURST is determined by the desired amount of output voltage ripple. As the value of IBURST increases, the sleep period between pulses and the output voltage ripple increase. The burst clamp voltage, VBURST, can be set by a resistor divider from the VFB pin to the SGND pin as shown in Figure 1. Pulse skipping, which is a compromise between low output voltage ripple and efficiency, can be implemented by connecting pin SYNC/MODEto ground. This sets IBURST to 0A. In this condition, the peak inductor current is limited by the minimum on-time of the current comparator. The lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. Frequency Synchronization The LTC3412A's internal oscillator can be synchronized to an external clock signal. During synchronization, the top MOSFET turn-on is locked to the falling edge of the external frequency source. The synchronization frequency range is 300kHz to 4MHz. Synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. Because slope compensation is generated by the oscillator's RC circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. Soft-Start The RUN/SS pin provides a means to shut down the LTC3412A as well as a timer for soft-start. Pulling the RUN/SS pin below 0.5V places the LTC3412A in a low quiescent current shutdown state (IQ < 1A). The LTC3412A contains an internal soft-start clamp that gradually raises the clamp on ITH after the RUN/SS pin is pulled above 2V. The full current range becomes available on ITH after 1024 switching cycles. If a longer soft-start period is desired, the clamp on ITH can be set externally with a resistor and capacitor on the RUN/SS pin as shown in Figure 1. The soft-start duration can be calculated by using the following formula: t SS = RSS CSS ln VIN (SECONDS) VIN - 1.8V
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LTC3412A
APPLICATIO S I FOR ATIO
Efficiency Considerations
The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN; thus, their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics
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curves. To obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Thermal Considerations In most applications, the LTC3412A does not dissipate much heat due to its high efficiency. However, in applications where the LTC3412A is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3412A from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: tr = (PD)(JA) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. For the 16-lead exposed TSSOP package, the JA is 38C/W. For the 16-lead QFN package the JA is 34C/W. The junction temperature, TJ, is given by: TJ = TA + tr where TA is the ambient temperature. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). To maximize the thermal performance of the LTC3412A, the exposed pad should be soldered to a ground plane. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current.
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LTC3412A
APPLICATIO S I FOR ATIO
When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in Figure 1 will provide adequate compensation for most applications. Design Example As a design example, consider using the LTC3412A in an application with the following specifications: VIN = 3.3V, VOUT = 2.5V, IOUT(MAX) = 3A, IOUT(MIN) = 100mA, f = 1MHz. Because efficiency is important at both high and low load current, Burst Mode operation will be utilized. First, calculate the timing resistor: 3.08 * 1011 - 10k = 298k ROSC = 1* 106 Use a standard value of 294k. Next, calculate the inductor value for about 40% ripple current at maximum VIN: 2.5V 2.5V L= 1- = 0.51H (1MHz)(1.2A) 3.3V Using a 0.47H inductor results in a maximum ripple current of: 2.5V 2.5V IL = 1- = 1.29A (1MHz)(0.47H) 3.3V COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, two 100F ceramic capacitors will be used. CIN should be sized for a maximum current rating of: IRMS = (3A) 2.5V 3.3V 3.3V - 1= 1.29ARMS 2.5V
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Decoupling the PVIN and SVIN pins with two 22F capacitors is adequate for most applications. The burst clamp and output voltage can now be programmed by choosing the values of R1, R2, and R3. The voltage on pin MODE will be set to 0.50V by the resistor divider consisting of R2 and R3. According to the graph of Minimum Peak Inductor Current vs Burst Clamp Voltage in the Typical Performance Characteristics section, a burst clamp voltage of 0.5V will set the minimum inductor current, IBURST, to approximately 1.1A. If we set the sum of R2 and R3 to 185k, then the following equations can be solved: R2 + R3 = 185k R2 0.8V 1+ = R3 0.50V The two equations shown above result in the following values for R2 and R3: R2 = 69.8k , R3 = 115k. The value of R1 can now be determined by solving the following equation. 2.5V R1 1+ = 185k 0.8V R1 = 392k A value of 392k will be selected for R1. Figure 4 shows the complete schematic for this design example. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3412A. Check the following in your layout: 1. A ground plane is recommended. If a ground plane layer is not used, the signal and power grounds should be segregated with all small signal components returning to the SGND pin at one point which is then connected to the PGND pin close to the LTC3412A. 2. Connect the (+) terminal of the input capacitor(s), CIN, as close as possible to the PVIN pin. This capacitor provides the AC current into the internal power MOSFETs.
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LTC3412A
APPLICATIO S I FOR ATIO
3. Keep the switching node, SW, away from all sensitive small signal nodes. 4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. You can connect the copper areas to any DC net (PVIN, SVIN, VOUT, PGND, SGND, or any other DC rail in your system).
Top Figure 3. LTC3412A Layout Diagram
RPG 100k PGOOD CITH 330pF X7R RITH 17.4k CC 47pF
R3 115k
R2 69.8k ROSC 294k
RSS 2.2M
CSS 1000pF X7R 8
*VISHAY IHLP-2525CZ-01 **TDK 4532X5R0J107M
Figure 4. 3.3V to 2.5V, 3A Regulator at 1MHz, Burst Mode Operation
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5. Connect the VFB pin directly to the feedback resistors. The resistor divider must be connected between VOUT and SGND.
Bottom
CFF 22pF X5R R1 392k VIN 3.3V CIN3** 100F 1 SVIN PGOOD ITH PVIN SW SW 16 CIN1 22F 2 3 15 14 L1* 0.47H 4 5 LTC3412A 13 EFE PGND VFB PGND RT SW SW PVIN 11 10 9 CIN2 22F X5R 6.3V
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VOUT 2.5V 3A
6 SYNC/MODE 7 RUN SGND
COUT** 100F x2
GND
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LTC3412A
TYPICAL APPLICATIO S
1.2V, 3A, 1.5MHz 1mm Height Regulator Using All Ceramic Capacitors
VIN 3.3V C1 22pF X5R R1 95.3k
PGOOD CITH 1000pF X7R RITH 6.34k CC 22pF
RSS 2.2M
*COOPER SD10-R47 **TAIYO YUDEN AMK212BJ226MD-B
1.8V, 3A Step-Down Regulator at 1MHz, Burst Mode Operation
CIN3** 100F C1 47pF X5R R1 232k VIN 2.5V
PGOOD CITH 820pF X7R RITH 15k C2 47pF
R3 115k
RSS 2.2M
*VISHAY IHLP-2525CZ-01 **TDK C4532X5R0J107M
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11 RPG 100k
SVIN PGOOD ITH
PVIN SW SW
10 CIN1 10F X5R 6.3V
12 13
9 8
14 R2 187k ROSC 196k 15 16 1 CSS 1000pF X7R 2
LTC3412A 7 EUF PGND VFB PGND RT SW SYNC/MODE RUN SGND SW PVIN 4 3 CIN2 10F X5R 6.3V 5 6
L1* 0.47H
VOUT 1.2V 3A
COUT** 22F X3
GND
3412 TA01
1 RPG 100k
SVIN PGOOD ITH
PVIN SW
16 CIN1 22F X5R 6.3V
2 3
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4 R2 69.8k ROSC 294k 5 6 7 CSS 1000pF X7R 8
14 SW LTC3412A 13 EFE PGND PGND 12 11 10 9 CIN2 22F X5R 6.3V
VFB RT SW SYNC/MODE RUN SGND SW PVIN
L1 0.47H*
VOUT 1.8V 3A COUT** 100F x3
3412 TA02
GND
LTC3412A
TYPICAL APPLICATIO S
3.3V, 3A Step-Down Regulator at 2MHz, Forced Continuous Mode Operation
CIN3** 100F VIN 5V
PGOOD
CITH 820pF X7R RITH 7.5k CC 47pF R2 200k ROSC 137k
RSS 2.2M
*VISHAY IHLP-2525CZ-01 **TDK C4532X5R0J107M
PGOOD CITH 220pF X7R
RSS 2.2M
*COOPER SD20-R47 **SANYO POSCAP 4TPE150MAZB
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C1 22pF X5R R1 634k
1 RPG 100k
SVIN PGOOD ITH
PVIN SW SW
16 CIN1 22F X5R 6.3V
2 3 4
15 14
LTC3412A 13 EFE PGND VFB PGND RT SW SYNC/MODE RUN SGND SW PVIN 10 9 CIN2 22F X5R 6.3V 11 12
L1* 0.47H
5 6 7
VOUT 3.3V 3A
COUT** 100F x2
CSS 1000pF X7R 8
GND
3412 TA03
2.5V, 3A Step-Down Regulator Synchronized to 1.8MHz
VIN 3.3V C1 22pF X5R R1 392k
1 RPG 100k RITH 6.49k
SVIN PGOOD ITH
PVIN SW
16 CIN1 22F X5R 6.3V
2 3
15
CC 22pF 4 R2 162k 5 ROSC 182k RT VFB
14 SW LTC3412A 13 EFE PGND PGND SW SW PVIN 12 11 10 9 CIN2 22F X5R 6.3V
L1* 0.47H
VOUT 1.5V 3A
1.8MHz 6 SYNC/MODE EXT CLOCK 7 RUN CSS 1000pF X7R 8 SGND
+
COUT** 150F
GND
3412 TA04
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LTC3412A
PACKAGE DESCRIPTIO
2.74 (.108)
6.60 0.10 4.50 0.10
SEE NOTE 4
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
4.30 - 4.50* (.169 - .177)
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
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FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 - 5.10* (.193 - .201) 2.74 (.108) 16 1514 13 12 1110 9
2.74 (.108) 0.45 0.05 1.05 0.10 2.74 6.40 (.108) (.252) BSC
12345678 1.10 (.0433) MAX
0 - 8
0.25 REF
0.65 (.0256) BSC
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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PACKAGE DESCRIPTIO
4.35 0.05 2.15 0.05 2.90 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 x 45 CHAMFER
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UF Package 16-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 0.05 PACKAGE OUTLINE 0.30 0.05 0.65 BSC 15 16 0.55 0.20 1 2.15 0.10 (4-SIDES) 2
(UF16) QFN 10-04
0.200 REF 0.00 - 0.05
0.30 0.05 0.65 BSC
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LTC3412A
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ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0708 REV C * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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